DocumentCode :
2993090
Title :
3-stage variable length continuous-flow scan vector decompression scheme
Author :
Krishna, C.V. ; Touba, Nur A.
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear :
2004
fDate :
25-29 April 2004
Firstpage :
79
Lastpage :
86
Abstract :
This paper presents a 3-stage continuous-flow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3-stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are left as don´t cares) regardless of the number of specified (care) bits. As a result of this feature, there is no need for any constraints on the automatic test generation process (ATPG). Any ATPG can be used with any amount of static or dynamic compaction. Experimental results are shown which demonstrate that the proposed scheme achieves extremely high encoding efficiency.
Keywords :
automatic test pattern generation; data compression; encoding; shift registers; variable length codes; 3-stage continuous flow scan vector decompression; automatic test generation process; deterministic test vector; dynamic compaction; static compaction; test cube; variable length continuous flow scan vector decompression; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Compaction; Encoding; Memory; Sequential analysis; Test data compression; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2134-7
Type :
conf
DOI :
10.1109/VTEST.2004.1299229
Filename :
1299229
Link To Document :
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