The effect of STI and active length on dual gate oxide reliability

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip. It has been found that the Qbd value of nMOS STI edge intensive capacitors for 12.5 nm oxide was nearly one order lower than the rest of the test structure design. Failure analysis using emission microscopy and SEM showed that the oxide breakdown occurred near STI shoulder. The STI effect was evaluated using various active lengths of test structures. The appropriate STI edge intensive test structure for 12.5 nm oxide GOI qualification was designed and verified.