An implemented architecture of deblocking filter for H.264/AVC

H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. We propose an efficient processing order for the deblocking filter, and present the VLSI architecture according to the order. Making good use of data dependence between neighboring 4×4 blocks, our design reduces the requirement of on-chip SRAM bandwidth and increases the throughput of the filter processing. The architecture has been described in Verilog HDL, simulated with VCS and synthesized using 0.25 μm CMOS cells library by Synopsys Design Compiler. The circuit costs about 24k logic gates (not including a 32×64 SRAM and two 32×96 SRAMs) when the working frequency is set to 100 MHz. This design can support real-time deblocking of HDTV (1280×720, 60 fps) H.264/AVC video. This architecture is valuable for the hardware design of an H.264/AVC codec.