DocumentCode :
2993304
Title :
Reducing bus delay in submicron technology using coding
Author :
Sotiriadis, Paul P. ; Chandrakasan, Anantha
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear :
2001
fDate :
2001
Firstpage :
109
Lastpage :
114
Abstract :
In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2
Keywords :
VLSI; coupled circuits; delays; distributed parameter networks; integrated circuit design; Elmore delay; coding; data patterns; distributed coupling component; distributed model; submicron technology; transitions; Couplings; Delay effects; Delay estimation; Differential equations; Encoding; Laplace equations; Noise figure; Parasitic capacitance; Voltage; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
Type :
conf
DOI :
10.1109/ASPDAC.2001.913289
Filename :
913289
Link To Document :
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