Optimization of ceramic packages including thermal via-hole for light emitting diode

Thermal via holes must be designed to emit the high heat flux generated from high power light emitting diodes (HP LEDs) that are 1000 times smaller than conventional electronics devices such as central processing unit (CPU). Therefore, it is important to layout via holes in accordance with the kinds of the devices. In this paper, we compare the performance of the packages with the three classes of via holes by verifying thermal resistance by using MicRed T3Ster and FLIR IR Camera. It is demonstrated that the large via hole beneath high power light emitting diode is superior to many scattered via holes under condition of the similar amount of silver paste for via filling. Detailed thermal performance is analyzed using CFD (computational fluid dynamics) technology and then verified with thermal resistance and heat distribution in printed circuit board (PCB) where light emitting diode (LED) packaging without the encapsulating material is implemented and then, the evaluation and the compensation of the errors for the process factor of the simulation are simultaneously accomplished. Thermal resistance of the packages with HEP (heat emission pole) is 5 ~ 13.8 times smaller than the others. The calculation formula of thermal conductivity is improved into a new equivalent formula with the device size, package size and the overlap area. The optimized via hole decreases the manufacturing cost while it increases the efficiency of the heat emission.