The output permutation for the multiple-valued logic minimization with universal literals

Author

Hozumi, Takahiro ; Kakusho, Osamu ; Hata, Yutaka

Author_Institution

Dept. of Econ. & Inf. Sci., Hyogo Univ., Japan

fYear

1999

fDate

1999

Firstpage

105

Lastpage

109

Abstract

This paper shows the effectiveness of an output permutation for the implementation of current-mode CMOS circuits. A combination of a simple function and an output permutation can realize a difficult function and cost for the combination will be lower than the cost for a difficult function. The output permutation can be realized by a universal literal and we can calculate the cost. We first examine the all combinations of universal literals and output permutations and show that some combinations can realize one-variable functions with lower costs. Next, we minimize two-variable functions and compare the costs with the costs obtained by some output permutations. As a result, we show that about 70% functions can reduce the costs and their reduction ratio is about 12% on average

Keywords

CMOS logic circuits; current-mode logic; minimisation of switching nets; multivalued logic; current-mode CMOS circuits; multiple-valued logic minimization; output permutation; two-variable functions; universal literal; universal literals; CMOS logic circuits; CMOS technology; Circuit synthesis; Cost function; Information science; Logic functions; Minimization methods; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1999. Proceedings. 1999 29th IEEE International Symposium on

Conference_Location

Freiburg

ISSN

0195-623X

Print_ISBN

0-7695-0161-3

Type

conf

DOI

10.1109/ISMVL.1999.779703

Filename

779703