Title :
Construction of minimal delay Steiner tree using two-pole delay model
Author :
Lin, LiYi ; Liu, YiYu ; Hwang, TingTing
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
In this paper, we study the construction of a Steiner routing tree for a given net with the objective of minimizing the delay of the routing tree. Previous researches adopt Elmore delay model to compute delay. However, with the advancement of IC technology, a more accurate delay model is required. Therefore, in this paper, we use the two-pole delay model to compute the cost function of a Steiner tree. Moreover, we propose a new algorithm to construct the Steiner tree. Our algorithm takes into consideration the net topology, the total wire length and the longest path from the source to sink. Experimental results show that our algorithm is very effective and efficient as compared to that used by Boese et al. (1995)
Keywords :
circuit layout CAD; delay estimation; integrated circuit interconnections; integrated circuit layout; network routing; trees (mathematics); Steiner routing tree; cost function; delay minimization; minimal delay Steiner tree; net topology; total wire length; two-pole delay model; Computer science; Cost function; Delay effects; Delay estimation; Inductance; Integrated circuit modeling; Routing; Steiner trees; Topology; Wire;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913292