Multicore-Aware Code Positioning to Improve Worst-Case Performance

Inter-thread interferences in shared caches can significantly affect the worst-case execution time (WCET) of real-time tasks running on multi-core chips. In this paper, we study three multicore-aware code positioning methods to reduce the inter-core L2 cache interferences between co-running real-time threads. One strategy focuses on decreasing the longest WCET among the co-running threads, and two other methods aim at achieving fairness in terms of the amount or percentage of WCET reduction among co-running threads. Our experiments indicate that the proposed multicore-aware code positioning approaches not only improve the worst-case performance of the real-time threads, but also make tradeoffs between efficiency and fairness for threads running on multi-core platforms.