DocumentCode
2993550
Title
Design of the High-Speed A/D Sampling Control Circuit Basing on FPGA
Author
Dong, Hongyan ; Guo, Hongmin
Author_Institution
Coll. Of Electr. Enineering & Inf. Technol., China Three Gorges Univ., Yichang, China
fYear
2010
fDate
25-27 June 2010
Firstpage
790
Lastpage
792
Abstract
This design describe a sample control process according to sampling sequence with MAX+PLUSII software and the VHDL language tool. The author takes TLC5510 as example, introduces a kind of designing method of the A/D sampling control circuit basing on the high-speed FPGA. The result of simulation expresses that the high-speed data collecting system have reached an expectant function.
Keywords
analogue-digital conversion; field programmable gate arrays; MAX+PLUSII software; VHDL language tool; expectant function; high-speed A/D sampling control circuit design; high-speed FPGA; high-speed data collecting system; sample control process; sampling sequence; CMOS integrated circuits; Clocks; Control engineering; Data models; Field programmable gate arrays; Presses; Random access memory; FIFO; FPGA; MAX+PLUSII; TLC5510; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Control Engineering (ICECE), 2010 International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-6880-5
Type
conf
DOI
10.1109/iCECE.2010.202
Filename
5630542
Link To Document