Memory BIST using ESP

A memory BIST enhancement, ESP short for exercising system paths, is described that allows the efficiency and functional capabilities of standard approaches while addressing two important problems. Conventional Memory BIST techniques require MUXes at the inputs of the memory that allow for the inputs to be driven either by system signals or by test signals. These MUXes add delays, in the system path going to the memory, which often has critical timing. ESP eliminates such delays by implementing the MUXing function ´before´ scan cells. ESP also uses scan cells to capture the memory output for feeding back to the BIST controller. This output may have traveled through some logic before getting to the recording scan cells. By including the delays of the system input and output paths, ESP allows for verifying that the memory will work correctly as part of the system rather than just as an isolated unit. Using ESP, a memory BIST can catch transition and delay faults that are impractical, or even impossible, to catch otherwise. Therefore, ESP can be useful for all memories but may be crucial for the memories which cannot tolerate the addition of the MUX delay to functional paths.