DocumentCode
2993571
Title
Application Of Ultra Low Loop gold wire bonding technique in Super Thin (Jedec Package Profile Height Sub Code “X2”) Quad Flat No Lead Package (QFN)
Author
Tan Boo Wei ; Wang Lei ; Niu, K. ; Lu Hai Long
Author_Institution
Carsem Semicond. (Suzhou) Co., Ltd., Suzhou, China
fYear
2008
fDate
4-6 Nov. 2008
Firstpage
1
Lastpage
6
Abstract
Quad Flat No Lead Package (QFN) with “Super Thin” package height of 0.3 to 0.4 mm (package profile height sub code “X2” per Jedec Standard) is designed with limited vertical space for wire loop height. Typical package construction consists of leadframe thickness, chip and chip attach adhesive thickness, mold (encapsulation) thickness left only 75 to 100 um (3 to 4 mils) space between chip surface and package surface which is available for wire bonding . Therefore wire bonding loop height in QFN-X2 package are typically controlled within less than 100um (4mils) as measured from chip surface to highest point of wire loop . Typically there are 3 areas to consider when developing gold wire bond techniques to achieve low loop height: 1. Stress level at the heat affected zone near wire exit above ball (1st bonds). 2. Consistency of wire loop height across all wires within same package. 3. Resistance to mold flow sweeping during molding (encapsulation process). There are two common wire bond techniques available to achieve wire loop height less than 100um (4mils) - bond stitch on ball (BSOB) and ultra low loop (ULL) forward bonding. This paper discusses the comparative performance and limitations of both wire bond techniques .
Keywords
bonding processes; electronics packaging; gold; moulding; Jedec package profile height sub code; QFN-X2 package; bond stitch on ball; chip attach adhesive thickness; encapsulation process; leadframe thickness; mold thickness; size 0.3 mm to 0.4 mm; super thin quad flat no lead package; ultralow loop forward bonding; ultralow loop gold wire bonding technique; wire bonding loop height; Bonding; Encapsulation; Gold; Heat transfer; Motion control; Neck; Semiconductor device packaging; Shape control; Stress; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Manufacturing Technology Symposium (IEMT), 2008 33rd IEEE/CPMT International
Conference_Location
Penang
ISSN
1089-8190
Print_ISBN
978-1-4244-3392-6
Electronic_ISBN
1089-8190
Type
conf
DOI
10.1109/IEMT.2008.5507845
Filename
5507845
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