Queue Time Impact on Defectivity at Post Copper Barrier Seed, Electrochemical Plating, Anneals and Chemical Mechanical Polishing

As design rules shrink beyond 0.1.3 mum the development focus has been a gradual shift in the defectivity on copper electroplating integrated circuit manufacturing applications. Effective process inspection and defect identification are key issues for the failure mechanisms in semiconductor manufacturing. In this paper, copper deposition with He in-situ and furnace anneal splits were performed on the Applied Materials SlimCell^TM ECP system. The paper outlines the queue time challenges from a defectivity perspective and the solutions implemented that addresses each issue. The analytical techniques used to classify these defects and the methods used to determine their origin is discussed. This paper will attempt to describe the impact of queue time on defectivity challenges and we introduce a new defect characterization scheme that takes the defect generation mechanism and the potential source into account. Further investigation implemented to study the possibility of imposing a time window between seed deposition and plating, plating to anneal duration as well as anneal to CMP in order to posed a significant challenge in differentiating between plating and CMP induced defects. Most defects were observed after chemical-mechanical planarization (CMP) was performed and defects that were generally categorized as missing copper could have resulted from corrosion, from scratches during CMP process from incomplete filling of fine features after plating.