Title :
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
Author :
Yang, Zhaozhi ; Wang, Zeyi ; Fang, Shuzhou
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor
Keywords :
VLSI; boundary integral equations; capacitance; circuit analysis computing; circuit layout CAD; computational complexity; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; VLSI parasitic interconnect capacitance; computational complexity reduction; indirect boundary integral equations; mesh charge distribution; multipole-accelerated algorithm; parasitic capacitance extractor; plane charge distribution; virtual 3D multipole accelerated extractor; Acceleration; Computational complexity; Computer science; Conductors; Delay; Integral equations; Integrated circuit interconnections; Parasitic capacitance; Very large scale integration; Wires;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913307
