DSP coprocessor cell for systolic arrays

Implementation of systolic arrays has been hindered in the past due to a lack of efficient building blocks, or cells, on silicon. The authors present a DSP coprocessor cell for rapid computation of elementary functions. For signal and image processing systolic arrays, several elementary functions typically need to be computed while the interconnection considerations as well as development costs warrant the use of as few types of cells as possible. With the present approach, all of the desired elementary functions can be realized in hardware on a single cell. A 16 bit four-function VLSI chip and an application example-a tracking version of singular-value decomposition, are presented