Title :
Boundary scan for 5-GHz RF pins using LC isolation networks
Author :
Huang, Tian-Wei ; Wu, Pei-Si ; Liu, Ren-Chieh ; Tsai, Jeng-Han ; Wang, Huei ; Chiueh, Tzi-Dar
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
The boundary-scan test provides a structural test solution for the densely packed digital electronics. For RF devices, the structural test also provides a good diagnostic resolution to the structural defects of RF circuits, especially for the high pin-count RF-SOCs. In this paper, the boundary-scan test is implemented on a 5-GHz RF pin using LC isolation networks to connect the RF lines and the boundary-scan cell, which isolates the RF circuitry from the digital boundary scan cell. This technique overcomes the parasitic loading problems and provides a minimum RF performance degradation to a RFIC. The measurement results show only 0.4-dB gain degradation in a 5-GHz amplifier with a boundary-scan cell and LC isolation networks.
Keywords :
CMOS integrated circuits; boundary scan testing; integrated circuit testing; radiofrequency amplifiers; radiofrequency integrated circuits; system-on-chip; 0.4 dB; 5 GHz; CMOS integrated circuits; LC isolation networks; RF SOC; RF circuit structural defects; RF devices; RF performance degradation; RF pins; RFIC; amplifier; boundary scan test; densely packed digital electronics; digital boundary scan cell; gain degradation; parasitic loading problems; structural test solution; Circuit testing; Costs; Degradation; Electronic equipment testing; Gain measurement; Manufacturing; Packaging; Pins; Radio frequency; Radiofrequency integrated circuits;
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
Print_ISBN :
0-7695-2134-7
DOI :
10.1109/VTEST.2004.1299263