Hybrid BIST for system-on-a-chip using an embedded FPGA core

In this paper, a novel hybrid built-in self-test (BIST) approach for system-on-a-chip (SOC) test using an embedded FPGA core is presented. The hybrid BIST combining pseudorandom test with deterministic test can achieve not only complete fault coverage but also minimal test cost by selecting the appropriate number of pseudorandom patterns. Most importantly, the FPGA-based hybrid BIST has minimal hardware overhead, since after testing, the FPGA core can be reconfigured as normal mission logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.