Defect-aware SOC test scheduling

In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests are performed until completion, we consider the cases where the test process are terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time is minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. concurrent scheduling), and test set assumptions (fixed test time vs. flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling.