DocumentCode :
2994007
Title :
Efficient ATPG for design validation based on partitioned state exploration histories
Author :
Wu, Qingwei ; Hsiao, Michael S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fYear :
2004
fDate :
25-29 April 2004
Firstpage :
389
Lastpage :
394
Abstract :
This paper introduces a new concept of state partitioning and state/transition exploration histories to generate test stimulus for the purpose of design validation. With our new state partitioning, during vector generation, state and transition exploration histories for each state group are maintained by dynamically constructing partial state transition graphs (STGs) for all state groups. By limiting a maximum size any state group can be, maintaining the complete state and transition exploration histories for each state group is feasible even for very large sequential circuits. While such histories are being collected, test vectors are generated using extracted spectral information from existing tests and genetic algorithm (GA) is used to explore new scenarios that are not in the histories. Experiments showed that much higher design error coverages together with smaller test sets are achieved with very short execution times.
Keywords :
automatic test pattern generation; data flow graphs; genetic algorithms; logic partitioning; sequential circuits; ATPG; execution time; genetic algorithm; partial state transition graphs; partitioned state exploration; sequential circuits; state partitioning; test stimulus generation; test vector generation; transition exploration; Automatic test pattern generation; Circuit testing; Concrete; Flip-flops; Formal verification; History; Logic design; Logic testing; Sequential circuits; State-space methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2134-7
Type :
conf
DOI :
10.1109/VTEST.2004.1299269
Filename :
1299269
Link To Document :
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