DocumentCode
2994051
Title
Low power design challenges for the decade
Author
Borkar, Shekhar
Author_Institution
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
2001
Firstpage
293
Lastpage
296
Abstract
Technology scaling will become difficult beyond 0.18 micron. For continued growth in performance, transistor density, and reduced energy per computation, circuit design will have to employ a new set of design techniques, with adequate design automation tools support. This paper discusses a few such techniques that reduce active and leakage power, and deliver higher performance. It concludes by pointing out some of the potential paradigm shifts
Keywords
electronic design automation; integrated circuit design; low-power electronics; active power; circuit design; design automation tools; leakage power; low power design challenges; paradigm shifts; reduced energy per computation; technology scaling; transistor density; Circuit synthesis; Clocks; Design automation; Dynamic voltage scaling; Energy consumption; Frequency; Logic; Microarchitecture; Microprocessors; Moore´s Law;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-6633-6
Type
conf
DOI
10.1109/ASPDAC.2001.913321
Filename
913321
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