Reducing cache energy through dual voltage supply

Due to a large capacitance and enormous access rate, caches dissipate about a third of the total energy consumed by today´s processors. In this paper we present a new architectural technique to reduce energy consumption in caches. Unlike previous approaches, which have focused on lowering cache capacitance and the number of accesses, our method exploits a new freedom in cache design, namely the voltage per access. Since in modern caches, the loading capacitance operated on cache-hit is much less than the capacitance operated on cache-miss, the given clock cycle time is inefficiently exploited during the hit. We propose to trade-off this unused time with the supply voltage, lowering the voltage level on the hit and increasing it during the miss. Experiments shows that the approach can save up to 60% of cache energy without large performance and area overhead