DocumentCode
2994194
Title
Design of fast connected components hardware
Author
Yang, Xue Dong
Author_Institution
Courant Inst. of Math. Sci., New York Univ., NY, USA
fYear
1988
fDate
5-9 Jun 1988
Firstpage
937
Lastpage
944
Abstract
The intensive use of the connected components algorithms in image analysis and robot vision calls for a very fast implementation of such algorithms suitable for real-time applications. A hardware design is presented which implements the algorithm due to J.T. Schwartz, M. Sharir, and A. Siegel (1985). A prototype board, which does not use special VLSI chips, had been constructed previously that can compute the connected components in a 512×512 binary image in few video frame times (about 300 ms). A real-time version (video speed) in VLSI is proposed
Keywords
VLSI; computer vision; parallel architectures; 26144 pixel; 512 pixel; VLSI; computer vision; connected components hardware; image analysis; parallel architectures; robot vision; Algorithm design and analysis; Application software; Computer science; Hardware; Image analysis; Laboratories; Pixel; Prototypes; Robot vision systems; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Vision and Pattern Recognition, 1988. Proceedings CVPR '88., Computer Society Conference on
Conference_Location
Ann Arbor, MI
ISSN
1063-6919
Print_ISBN
0-8186-0862-5
Type
conf
DOI
10.1109/CVPR.1988.196345
Filename
196345
Link To Document