Parallel bit-level pipelined VLSI processing unit for the histogramming operation

Using the odd-even network topology, a parallel bit-level pipelined VLSI processing unit is designed for the histogramming operation. In this approach, histogramming is divided into two stages, the counting and marking process and the filtering process. The filtering process is computationally inexpensive compared to the counting and marking phase. The proposed processing unit is composed of one type of bit-serial structure (processing element) operating in parallel. The architecture and VLSI implementation of the processing unit is considered. The performance of the design is compared with the implementation of the histogramming operation on the Massively Parallel Processor. The comparative analysis shows that the odd-even network based approach has significant advantages in terms of both processing speed and performance/cost ratio