• DocumentCode
    299428
  • Title

    Real-time signal preprocessor trade-off study

  • Author

    Hill, Kerry L. ; Foti, Laurn C. ; Zebe, David B. ; Box, Brian A.

  • Author_Institution
    WL/AAAT-2, USA
  • Volume
    1
  • fYear
    1995
  • fDate
    22-26 May 1995
  • Firstpage
    328
  • Abstract
    Signal preprocessing for avionics systems has typically consisted of custom hard-wired solutions which offer high performance but little design flexibility. Recently, a preprocessor trade-off study for an infrared (IR) application evaluated two advanced processing architectures both of which can provide not only high-performance, but also design flexibility. The objective of the study was to determine the best preprocessing solution for the Medium Wave IR Array (MIRA) system based on algorithm performance, processing density, “programmability”, cost, and schedule. This study is based on the implementation of two IR algorithms each separately executed and evaluated on both of the architectures. The two architectures which were evaluated are the Lockheed Sanders Configurable-Hardware Algorithm-Mappable Preprocessor (CHAMP), developed under contract with the Wright Laboratory Avionics Directorate, and the Texas Instruments (TI) TMS320C80 Digital Signal Processor. In the last decade, the hardware community has seen the introduction of the field programmable gate array (FPGA) which offers fast reconfigurability and high performance. The CHAMP preprocessor architecture, which is based on FPGA technology, was conceived to produce an alternative preprocessor that can provide high-performance, implementation flexibility, low cost, and a much reduced development cycle. CHAMP provides up to 4 BOPS on a double-sided 6U VME board. CHAMP technology is applicable to preprocessing for IR, forward looking IR (FLIR), imaging, including magnetic resonance imaging (MRI) and mammography, and automatic target recognition (ATR). Recent improvements in the DSP arena, particularly in packaging and performance, have made DSP architectures much more competitive. Texas Instruments (TI) has developed the Multimedia Video Processor (MVP) also known as the TMS320C80 Digital Signal Processor. It is rated at 2 BOPS and is a fully programmable digital signal processor. The MVP architecture contains four integer DSPs as well as a specialized RISC processor. The MVP is targeted for telecommunications, video, graphics, imaging, and audio applications
  • Keywords
    aerospace computing; avionics; digital signal processing chips; field programmable gate arrays; image processing; image processing equipment; infrared imaging; multimedia computing; real-time systems; reconfigurable architectures; CHAMP preprocessor architecture; FLIR; FPGA; Lockheed Sanders Configurable-Hardware Algorithm-Mappable Preprocessor; Medium Wave IR Array; Multimedia Video Processor; RISC processor; TMS320C80 Digital Signal Processor; Texas Instruments; Wright Laboratory; algorithm performance; avionics; cost; field programmable gate array; magnetic resonance imaging; mammography; programmability; real-time signal preprocessor; reconfigurability; signal preprocessing; video; Aerospace electronics; Costs; Digital signal processing; Digital signal processors; Field programmable gate arrays; Instruments; Magnetic resonance imaging; Scheduling algorithm; Signal design; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Aerospace and Electronics Conference, 1995. NAECON 1995., Proceedings of the IEEE 1995 National
  • Conference_Location
    Dayton, OH
  • ISSN
    0547-3578
  • Print_ISBN
    0-7803-2666-0
  • Type

    conf

  • DOI
    10.1109/NAECON.1995.521960
  • Filename
    521960