Title :
Formal verification of pulse-mode asynchronous circuits
Author :
Kong, Xiaohua ; Negulescu, Radu
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existing technique for verifying asynchronous circuits under relative timing constraints at several levels of abstraction
Keywords :
asynchronous circuits; clocks; formal verification; integrated circuit modelling; logic CAD; timing; abstraction; asynchronous design styles; formal verification; functional models; pulse-mode asynchronous circuits; pulse-mode circuits; Asynchronous circuits; Circuit synthesis; Clocks; Formal verification; Integrated circuit synthesis; Propagation delay; Protocols; Pulse circuits; Space vector pulse width modulation; Timing;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913331
