Title :
Post-layout transistor sizing for power reduction in cell-based design
Author :
Hashimoto, Masanori ; Onodera, Hidetoshi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using five circuits. The power dissipation is reduced by 77% maximum and 65% on average without delay increase
Keywords :
MOS digital integrated circuits; application specific integrated circuits; cellular arrays; delays; integrated circuit design; integrated circuit modelling; low-power electronics; redundancy; MOSFETs; cell-based circuits; cell-based design; delay increase; detail-routed circuits; post-layout transistor sizing; power dissipation; power reduction; redundancy; Capacitance; Compaction; Delay effects; Integrated circuit interconnections; MOSFETs; Pins; Power dissipation; Redundancy; Routing; Wire;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913333
