Title :
An efficient new systolic architecture for the solution of discrete Fourier transform
Author :
Baghaie, Ramin ; Hartimo, Iiro
Author_Institution :
Lab. of Signal Process. & Comput. Technol., Helsinki Univ. of Technol., Espoo, Finland
Abstract :
By using the even-odd decomposition method, an efficient word level systolic array for implementation of an N-point discrete Fourier transforms (DFT) has been developed. With the aid of a 4-point pre-processor consisting of some simple adders, implementation of a fully-pipelined N-point DFT can be achieved by using only (N/4 + 1) CORDIC processing elements. One of the features of this architecture is that no index mapping is required. Having throughput of O(N), hardware requirements are reduced by a factor of four compare to other systolic implementations with the same throughput
Keywords :
VLSI; discrete Fourier transforms; parallel algorithms; pipeline arithmetic; systolic arrays; 4-point pre-processor; CORDIC; VLSI; adders; discrete Fourier transform; efficient word level systolic array; even-odd decomposition method; fully-pipelined; reduced hardware requirement; systolic architecture; Computer architecture; Digital signal processing; Discrete Fourier transforms; Equations; Hardware; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration;
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
DOI :
10.1109/VLSISP.1993.404460