DocumentCode :
2994564
Title :
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
Author :
Sretasereekul, Nattha ; Nanya, Takashi
Author_Institution :
Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan
fYear :
2001
fDate :
2001
Firstpage :
437
Lastpage :
442
Abstract :
The quasi-delay-insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be “isochronic” or can be even ignored
Keywords :
VLSI; asynchronous circuits; delays; logic gates; QDI circuits; forking branches; isochronic-fork constraints; quasi-delay-insensitive circuits; uniform switching thresholds; uniform wire delays; Delay; Digital circuits; Hazards; Inverters; Uncertainty; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
Type :
conf
DOI :
10.1109/ASPDAC.2001.913347
Filename :
913347
Link To Document :
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