Low-power high-level synthesis using latches

Author

Yang, Wooseung ; Park, In-Cheol ; Kyung, Chong-Min

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

2001

fDate

2001

Firstpage

462

Lastpage

465

Abstract

High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping dock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39-65% reduction in power consumption within almost the same area compared to the conventional power management scheme using clock gating

Keywords

clocks; flip-flops; high level synthesis; low-power electronics; storage allocation; clock gating; high-level synthesis systems; latches; low-power high-level synthesis; power consumption; power management scheme; single clocking scheme; storage allocation method; storage elements; Capacitance; Circuits; Clocks; Digital signal processing; Energy consumption; Energy management; Flip-flops; Frequency; High level synthesis; Latches;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913351

Filename

913351