6-b 1.6-GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18µm CMOS

This work presents a novel flash analog-to-digital converter (ADC) with distributed track-and-hold pre-comparators (THPCs). Utilizing the proposed architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18 mum CMOS process, a 1.6 GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400 fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81 dB, which is 5.66 ENOB at 1.6 GS/s with a 793.8 MHz input signal frequency. The proposed ADC consumes 300 mW from a 1.8-V supply at full operating speed.