High-speed reduced stack dual lock circuits

This paper proposes a new pipeline circuit design with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. The single-bit operating cycle has only 6 CMOS inversions of which the forward latency has only 2 inversions. In the multi-bit case, we eliminate acknowledge completion detection and we place the request completion detection outside critical paths while still preventing data overlap in both convergent and ring trajectories. An implementation in CMOS 0.18 μm exhibits a latency of 56 ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in a Hspice simulation. Reduced swing versions of the proposed circuits further improve these full-swing measurements.