On-chip power-on reset strategy and I/O power supply detection for VLSI circuits

Many of the complex VLSI systems have separate I/O and core supplies and follow a predefined power up sequence. In this paper, an on-chip power-on reset (POR) strategy and an I/O power supply detection circuit with low steady-state power consumption are proposed. Our technique allows the I/O power supply monitoring, independently from the core power supplies. The I/O power supply detection circuit can detect both ramp up and ramp down of the supply voltage and has a fixed detection threshold. The circuit can operate for any I/O supply voltage level ranging from 1.5 V to 3.3 V. Simulation results show a maximum steady state power consumption of 23 muW. Due to this fact the proposed POR circuit is suitable for low power applications and embedding in portable device systems.