Module placement with boundary constraints using the sequence-pair representation

Author

Lai, Jianbang ; Ming-Shiun Lin ; Ting-Chi Wang ; Wan, Li-C

Author_Institution

Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan

fYear

2001

fDate

2001

Firstpage

515

Lastpage

520

Abstract

In VLSI module placement, it is very practical to consider placing some modules along the pre-specified boundaries of the chip so that the modules are easier to be connected to certain I/O pads. In this paper, we study the module placement problem where some modules have boundary constraints, and present a simulated annealing based algorithm that represents each placement topology by a sequence-pair. The major contribution of our algorithm is that a feasible placement is always obtainable. Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results

Keywords

VLSI; circuit layout CAD; integrated circuit layout; simulated annealing; I/O pads; IC layout; VLSI module placement; boundary constraints; placement topology; pre-specified boundaries; sequence-pair representation; simulated annealing based algorithm; Algorithm design and analysis; Computational modeling; Cost function; Design methodology; Routing; Simulated annealing; Stochastic processes; Topology; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913360

Filename

913360