Title :
FAST-SP: a fast algorithm for block placement based on sequence pair
Author :
Tang, Xiaoping ; Wong, D.F.
Author_Institution :
Texas Univ., Austin, TX, USA
Abstract :
In this paper we present FAST-SP which is a fast block placement algorithm based on the sequence-pair placement representation. FAST-SP has two significant improvements over previous sequence-pair based placement algorithms: (1) FAST-SP translates each sequence pair to its corresponding block placement in O(n log log n) time based on a fast longest common subsequence computation. This is much faster than the traditional O(n2) method by first constructing horizontal and vertical constraint graphs and then performing longest path computations. As a result, FAST-SP can examine more sequence pairs and obtain a better placement solution in less runtime. (2) FAST-SP can handle placement constraints such as pre-placed constraint, range constraint, and boundary constraint. No previous sequence-pair based algorithms can handle range constraint and boundary constraint. Fast evaluation in O(n log log n) time is still valid in the presence of placement constraints and a novel cost function which unifies the evaluation of feasible and infeasible sequence pairs is used. We have implemented FAST-SP and obtained excellent experimental results. For all MCNC benchmark block placement problems, we have obtained the best results ever reported in the literature (including those reported by algorithms based on O-tree and B*-tree) with significantly less runtime. For example, the best known result for ami49 (36.8 mm2) was obtained by a B*-tree based algorithm using 4752 seconds, and FAST-SP obtained a better result (36.5 mm2 ) in 31 seconds
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; tree data structures; FAST-SP algorithm; VLSI layout; boundary constraint; cost function; fast block placement algorithm; fast longest common subsequence computation; placement constraint; pre-placed constraint; range constraint; runtime reduction; sequence pair based placement; sequence-pair placement representation; Circuit optimization; Conductors; Cost function; Design automation; Integrated circuit interconnections; Integrated circuit technology; Runtime; Simulated annealing; Transistors; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913361