Short circuit power estimation of static CMOS circuits

Author

Jung, Seung-Ho ; Baek, Jong-Humn ; Kim, Seok-Yoon

Author_Institution

Dept. of Comput., Soongsil Univ., Seoul, South Korea

fYear

2001

fDate

2001

Firstpage

545

Lastpage

549

Abstract

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution

Keywords

CMOS logic circuits; VLSI; capacitance; integrated circuit design; integrated circuit modelling; logic CAD; low-power electronics; CMOS logic circuits; actual current curves; gate-to-drain coupling capacitance; load capacitance; peak points; power dissipation; short circuit power estimation; signal transition time; static CMOS circuits; CMOS technology; Capacitance; Circuit simulation; Clocks; Coupling circuits; Delay estimation; Inverters; Power dissipation; Semiconductor device modeling; Short circuit currents;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913365

Filename

913365