Timing driven gate duplication in technology independent phase

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of a gate duplication strategy suggested previously (C. Chen and C. Tsui, 1999). Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization