Sample/Hold, V2I and output latching techniques for an asynchronous low area ADC

The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree structure exhibiting ultra low die area and power consumption will be presented in this paper. It is based on integer division that is implemented by current mode circuits that operate without a clock signal. Special emphasis is given on the description of the Sample/Hold and Voltage to Current conversion method at the input of such an asynchronous ADC as well as in the selection of an appropriate clock for the latching of correct codes at the ADC output and the relevant trade offs. The designed 8-bit ADC occupies 0.06 mm² area and dissipates 32 mW power while its active throughput is 150 MS/s.