• DocumentCode
    2995221
  • Title

    Power, speed and area comparison of several new DPT architectures

  • Author

    Hsiao, Shen-Fu ; Yen, Chung-Yi

  • Author_Institution
    Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
  • Volume
    4
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    2577
  • Abstract
    Two new pipelined and one constant-geometry DFT architectures are presented. The first pipelined DFT architecture is based on the conventional radix-2 pipelined FFT with modification to reduce by half the number of registers in the preprocessor. The second pipelined DFT is a modified version of the architecture proposed by Boriakoff in with the number of multipliers reduced by two-thirds. The constant-geometry DFT structure with hardware complexity independent of the transform length is derived from our new Boriakoff-like structure. Two different methods are used to estimate the speed, power and area performance of the above DFT architectures
  • Keywords
    computer architecture; digital signal processing chips; discrete Fourier transforms; pipeline processing; Boriakoff-like structure; area; constant-geometry DFT architecture; multiplier; pipelined DFT architecture; power; preprocessor; radix-2 pipelined FFT; register; speed; Arithmetic; Computer architecture; Discrete Fourier transforms; Hardware; Matrix converters; Matrix decomposition; Power engineering and energy; Power engineering computing; Switches; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.612851
  • Filename
    612851