Built-In Self-Test of embedded memory cores in Virtex-5 Field Programmable Gate Arrays

Author

Dailey, Justin L. ; Garrison, Brooks R. ; Pulukuri, Mary D. ; Stroud, Charles E.

Author_Institution

Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA

fYear

2011

fDate

14-16 March 2011

Firstpage

220

Lastpage

225

Abstract

This paper introduces and details a Built-In Self-Test (BIST) approach designed for the embedded Block Random Access Memories (BRAMs) found within Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). The BIST is designed to test the BRAMs in all configurable modes of operation including single-port, dual-port, first-in first-out (FIFO), first-in first-out with error correcting code (FIFOECC), and error correcting code (ECC) modes. The BIST architecture and implementation in actual Virtex-5 FPGAs will be discussed along with fault detection and timing analysis data taken from those implementations.

Keywords

built-in self test; error correction codes; field programmable gate arrays; integrated memory circuits; logic design; logic testing; random-access storage; FIFO; FPGA; Virtex-5 field programmable gate arrays; Xilinx; block random access memories; built-in self-test; embedded memory cores; error correcting code; fault detection; first-in first-out; timing analysis; Built-in self-test; Circuit faults; Error correction codes; Fault detection; Field programmable gate arrays; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on

Conference_Location

Auburn, AL

ISSN

0094-2898

Print_ISBN

978-1-4244-9594-8

Type

conf

DOI

10.1109/SSST.2011.5753810

Filename

5753810