Dynamic scan clock control in BIST circuits

We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented as on-chip hardware. Two models, one for test sets with peak activity factor of 1 and the other for test sets with peak activity factor lower than 1, have been proposed. In test sets with peak activity factors of 1, the test time reduction accomplished depends upon an average activity factor of α_in. For low α_in, about 50% test time reduction is analytically shown. With moderate activity, α_in = 0.5, simulated test data gives about 25% test time reduction for ITC02 benchmarks. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead. In test sets with peak activity factors lower than 1, the test time reduction depends on an input activity factor of α_in and an output activity factor of α_out. For low α_in and high α_out, a test time reduction of about 50% is analytically shown.