Efficient partial enhanced scan for high coverage delay testing

The architectural limitations of traditional scan restrict the two pattern delay tests that can be applied to a design, resulting in degraded delay test coverage. The use of enhanced scan flip-flops can alleviate this problem by supporting arbitrary delay test vector pairs, but at very high area overhead. Earlier work, using a Monte-Carlo simulation based flip-flop selection procedure on the smaller benchmark circuits has shown that most of the TDF coverage benefits of full enhanced scan can be achieved by using only 20-30% enhanced scan flip-flops. However, Monte-Carlo simulation to obtain signal probabilities to identify flip-flops that have poor controllability is not practical for large circuits. We present a new, computationally efficient method for selecting the enhanced scan flip-flops that leverages commercial testability tools by using easy to compute SCOAP testability measures. Furthermore, our method substantially improves on the earlier partial enhanced scan results by developing a methodology for eliminating some of the poor controllability flip-flops as candidates for enhanced scan through analysis of signal constraints due to the circuit structure. We also discover additional flip-flops that display strong dependencies between the V1 and V2 vectors during LOC tests that were missed in. The result is a computationally efficient selection method that identifies only those flip-flops where the dependency between the V1 and V2 vectors in LOC tests limits TDF coverage. Our results show that only 10-20% enhanced scan flip-flops can support high quality delay tests.