An Improved Bang-bang PLL Employing a Quaternary Phase Detector

This paper presents a bang-bang PLL architecture that employs two discrete loop gains depending on whether the magnitude of the PLL´s phase error is less than or greater than ¿/2. The advantage of this architecture is that the two loop gains can be used to independently optimize both pull-in range and jitter characteristics. A conservative expression to calculate pull-in range is derived and it is shown that pull-in range depends mainly on the PLL´s outer loop gain, thus freeing inner loop gain to control PLL dynamics when in lock.