DocumentCode :
2995512
Title :
Practical algorithm-based fault tolerant DFT system implementation on a hypercube multiprocessor
Author :
Sung, Jan-Lung ; Redinbo, G. Robert
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear :
1993
fDate :
20-22 Oct 1993
Firstpage :
397
Lastpage :
405
Abstract :
Most practical fast DFT systems with non-trivial N number sample points are generally implemented by only several processing units. Efficient time-sharing these few units and including low cost fault detection and reconfiguration is an important design issue for highly dependable DFT systems. The authors discuss achieving low cost fault detection for DFT system by scheduling the limited processing elements on a hypercube. To simplify the discussion, only radix-2 DFT systems are discussed, i.e., N will be always assumed as a power of 2
Keywords :
data flow computing; digital arithmetic; discrete Fourier transforms; error detection; fault tolerant computing; hypercube networks; parallel algorithms; processor scheduling; scheduling; algorithm-based; fault tolerant DFT system implementation; hypercube multiprocessor; low cost fault detection; radix-2 DFT systems; scheduling; Contracts; Costs; Discrete Fourier transforms; Fast Fourier transforms; Fault detection; Fault tolerance; Fault tolerant systems; Hypercubes; Power system protection; Processor scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
Type :
conf
DOI :
10.1109/VLSISP.1993.404466
Filename :
404466
Link To Document :
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