Title :
Design of DPLL used in SDH equipment clock
Author :
Shi, Guowei ; Zhai, Xiaojun ; Chen, Ming
Author_Institution :
Northwestern Polytech. Univ., Xian, China
Abstract :
Field programmable gate arrays (FPGA) have been widely used in the telecommunication field. This paper introduces the design principle of a highly stable digital phase locked loop (DPLL) used in SDH equipment clock (SEC). The main components of DPLL are implemented with FPGA. The chief test results obtained in our lab shows that the DPLL has an excellent performance in tracking the reference frequency
Keywords :
digital communication; digital phase locked loops; optical communication equipment; synchronous digital hierarchy; DPLL; SDH equipment clock; digital phase locked loop; reference frequency; tracking; Clocks; Detectors; Field programmable gate arrays; Frequency; Phase detection; Phase locked loops; Stability; Synchronous digital hierarchy; Timing jitter; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913401
