Title :
Hardware implementation of packet-fair queuing schedulers in high speed networks
Author :
Yang, Haijun ; Wang, Dawei ; Hong, Peilin ; Li, Jinsheng
Author_Institution :
Dept. of Electron. Eng. & Inf. Sci., Univ. of Sci. & Technol. of China, Hefei, China
Abstract :
Recently much research attention has been focused on implementing efficient per-flow scheduling mechanism in next generation ATM switches and routers to support the high speed multiplexing of a large number of flows with diverse traffic parameters and QoS requirements over the same network link. In this paper, we present an efficient FPGA design of packet-fair queuing schedulers based on discrete backlogged rates and packet lengths. According to the results of timing simulation, this design can process IP packets at 1.2 Gb/s which is fully capable of supporting two OC-12 POS media interfaces in high speed routers
Keywords :
broadband networks; data communication equipment; digital communication; field programmable gate arrays; multimedia communication; packet switching; quality of service; queueing theory; scheduling; telecommunication network routing; telecommunication traffic; timing; 1.2 Gbit/s; IP packets; OC-12 POS media interfaces; QoS requirements; discrete backlogged rates; efficient FPGA design; hardware implementation; high speed multiplexing; high speed networks; high speed routers; packet lengths; packet-fair queuing schedulers; scheduling mechanism; timing simulation; traffic parameters; traffic shaping; Asynchronous transfer mode; Field programmable gate arrays; Hardware; High-speed networks; Intelligent networks; Process design; Processor scheduling; Scheduling algorithm; Switches; Timing;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913406
