A new unified systolic array algorithm for discrete cosine and sine transforms with improved performances [and VLSI array implementation]

In this paper, a new approach for the realization of a unified VLSI array for discrete cosine and sine transforms (1D-DCT/DST) is presented. This approach is based on new computational relations for odd prime-length DST and DCT which uses two half-length cyclic convolutions having the same form and length which can be computed in parallel using hardware modules with the same structure and length. The proposed unified algorithm can be used to obtain a new unified systolic array with a very high percentage of the chip area being shared by the two transforms. Moreover, using this approach, a significant improvement of the performances of the hardware implementation of DCT/DST using systolic arrays can be obtained. Thus, the average computation time has been reduced to one half and the throughput has been doubled, as compared with configurations using a much simpler control structure, and having a simpler hardware structure. It owns also all the other outstanding features of the systolic arrays based on using cyclic convolutions proposed for DCT and DFT