DocumentCode
299585
Title
Performance evaluation of parallel concatenated codes
Author
Benedetto, Sergio ; Montorsi, Guido
Author_Institution
Dipartimento di Elettronica, Politecnico di Torino, Italy
Volume
2
fYear
1995
fDate
18-22 Jun 1995
Firstpage
663
Abstract
A parallel concatenated coding scheme consists of two simple systematic constituent encoders linked by an interleaver. The input bits to the first encoder are scrambled by the interleaver before entering the second encoder. The codeword of the parallel concatenated code consists of the input bits followed by the parity check bits of both encoders. The authors propose a method to evaluate the bit error probability of a parallel concatenated coding scheme in a way which is independent from the interleaver used. The two cases of parallel concatenated block codes and parallel concatenated convolutional codes are considered
Keywords
block codes; concatenated codes; convolutional codes; error statistics; interleaved codes; bit error probability; codeword; input bits; interleaver; parallel concatenated block codes; parallel concatenated codes; parallel concatenated convolutional codes; parity check bits; performance evaluation; scrambling; systematic constituent encoders; Block codes; Concatenated codes; Convolutional codes; Error probability; Hamming weight; Iterative algorithms; Iterative decoding; Parity check codes; Semiconductor device measurement; Turbo codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2486-2
Type
conf
DOI
10.1109/ICC.1995.524187
Filename
524187
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