Title :
Technology mapping for field-programmable gate arrays using integer programming
Author :
Chowdhary, A. ; Hayes, J.P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) or multiplexes. We also show that the MILP formulation can be easily modified to optimize area delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.
Keywords :
circuit CAD; field programmable gate arrays; integer programming; linear programming; logic CAD; logic partitioning; software prototyping; table lookup; area delay; benchmark circuits; field-programmable gate arrays; integer programming; logic block architectures; lookup tables; mixed integer linear programming problem; multiplexes; partitioning; technology mapping; truly optimal mappings; Computer architecture; Delay; Field programmable gate arrays; Laboratories; Linear programming; Logic circuits; Logic devices; Logic programming; Programmable logic arrays; Table lookup;
Conference_Titel :
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-8200-0
DOI :
10.1109/ICCAD.1995.480139