FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers

In this paper we present three different radix-10 digit recurrence division algorithms for FPGA architectures. The first one implements the simple shift-and-subtract algorithm, whereas the second and third implementations each perform digit recurrence algorithm with signed-digit redundant quotient alculation and carry-save representation of the residuals. However, the second divider computes the quotient digit using a ROM whereas the third divider uses a quotient digit decomposition and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA and implementation results are given.