Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

Author

Chen, Chuen-Yau ; Hsieh, Yuan-Ta ; Liu, Bin-Da

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2000

fDate

2000

Firstpage

148

Lastpage

151

Abstract

In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35 μm SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5 M FLIPS. The supply voltage of this system is 3.3V

Keywords

CMOS integrated circuits; VLSI; controllers; current-mode circuits; fuzzy control; mixed analogue-digital integrated circuits; pipeline processing; 0.35 micron; 3.3 V; SPQM CMOS process; circuit complexity; clocking strategy; current-mode approach; inference operation; level 28 model; linguistic hedge modifiers; mixed-signal VLSI design; pipelined mixed-signal fuzzy logic controller; programmable units; Circuit simulation; Clocks; Complexity theory; Digital circuits; Digital signal processing; Fuzzy logic; Process design; Semiconductor device modeling; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on

Conference_Location

Tianjin

Print_ISBN

0-7803-6253-5

Type

conf

DOI

10.1109/APCCAS.2000.913428

Filename

913428