Author :
Oliver, Neal ; Sharma, Rahul R. ; Chang, Stephen ; Chitlur, Bhushan ; Garcia, Elkin ; Grecco, Joseph ; Grier, Aaron ; Ijih, Nelson ; Liu, Yaping ; Marolia, Pratik ; Mitchel, Henry ; Subhaschandra, Suchit ; Sheiman, Arthur ; Whisonant, Tim ; Gupta, Prabhat
Abstract :
Typical reconfigurable computing systems are based on an I/O interconnect such as PCIe. This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of on-streaming-data applications unduly difficult. We describe an architecture based on Intel® Quick Path Interconnect® that addresses these concerns.
Keywords :
cache storage; field programmable gate arrays; reconfigurable architectures; I/O interconnect; Intel Quick Path Interconnect; PCIe; bandwidth performance; cache-coherent fabric; in-socket FPGA; on-streaming-data applications; packet sizes; reconfigurable computing system; Fabrics; Field programmable gate arrays; Hardware; Kernel; Memory management; Protocols; Reconfigurable computing; cache coherent; in-socket FPGA; shared virtual memory;
